AT056TN04 LCD Driver Controller

As a large screen resolution than analog, glass line will be more dense, the cost of higher technology and backlight, the color less demanding in the field of industrial instrumentation, low-cost analog color LCD screen has become the first choice. FPGA technology presents a color LCD drive controller design using hardware description language to complete the LCD timing and memory interfaces, the successful implementation of the 8 basic colors AT056TN04 display, both to overcome the color monotone monochrome LCD modules, color-rich expensive digital color screen shortcomings, but also has shown a small amount of data the user the advantages of simple operation. Appropriate adjustments can be easily applied to other analog color LCD screen, in the industrial instrumentation has good application value.
To make the products in the market competition in a strong position in the industrial instrumentation, the monochrome LCD color screen gradually being replaced is an inevitable trend. Since high resolution digital color screen, the glass will be more dense line, process and screen backlight will be higher cost than analog. Therefore, less demanding on the color of the field of industrial instrumentation, has become the preferred low-cost analog screen. The design of instrumentation for industrial applications in the background with a good group of record companies TFT analog LCD screen AT056TN04, using FPGA technology to achieve the drive controller design.
1 shows the memory arrangement
    LCD timing controller driver is in control of the system clock, line clock and frame synchronization clock synchronization under the control loop to put data in the display memory to the LCD screen, while under the control of the microprocessor memory data updates. To simplify the design, each color pixel LCD screen, 1 b are used to quantify 8 basic colors can be achieved, the circuit simple. To facilitate the structural arrangement, the LCD screen coordinates of upper left corner of the first point (0,0), lower right corner coordinates (233,319). 64 KB of SRAM used as a display memory, each memory cell, said the LCD screen 8 adjacent pixels of a color component, in which the red end of the address stored in the unit 00, the green is 01, blue 10. Although the waste end of the address is 11 units, addressing is very convenient. 16-bit address lines as the high 8-bit row address, the middle 6 bits for the column address, low address two of the colors.
2 Design of LCD driver timing
    AT056TN04 drive signals of the most important interface signals are: the frame start pulse STV, scan driver shift clock CKV, scan driver output enable control OEV, a common electrode driving signal Vcom, data-driven output enable control of OEH, line scanning start pulse STH, data sampling and the shift clock CPH. AT056TN04 display process is as follows: first, the frame start signal STV starts a data display, over time OEV tOEV from low to high maintenance and then high to low, while VCOM transitions, OEH and then descending to maintain tOEH transition from low to high, after tDIS1 STH after the transition from low to high, and then maintain tSTH transition from high to low to start the first line of the display. During this period CKV maintain tCKV from low to high after the high to low. Line after completion, and then replaced one line display, so to repeat down. After a frame data, and then the cycle of this process, the details of the timing shown in Figure 1.
    Figure in all time intervals are integer multiple of CPH, CPH therefore count with the counter tcph on to determine the value of tcph other control signals can be generated, while ensuring that each group signal synchronization. Time requirements of the interface signals in AT056TN04 has been given in the manual, CPH is the smallest unit of the timing, the cycle is 154 ns, the error can not exceed 4 ns. Active with 13 MHz crystal clock cycle 76.9 ns, its divided by 2 to get the CPH 153.8 ns clock. AT056TN04 each frame contains 256 ~ 268 lines of data, the real number is 234-line display line, the last of the small number of lines of data is not displayed. External controller can not display the data in these rows in the display memory read and write operations. The design of the data shows the number of lines per frame is set to 260 lines, then STV is that every line will produce a pulse of 260, with a line counter th, when tcpvh 260 (the line shows end) plus 1, after th, to generate STV, STV appears to delay tSV (3 lines)
3 LCD screen refresh module design
    AT056TN04 configured to scan from left to right from top to bottom, each time point into the memory 8 tri-color information (3 B), CPH clock every three bytes of RGB data simultaneously to the left one, in The RGB output pin connected PFGA 4.7 kΩ pull-up resistor to 5 V power supply, resulting in VR, VG, VB signal drive the LCD screen. In the RAM read and write control module under the action and timing module in the controller will display RAM to the cycle of image data displayed on the LCD screen. Th and tcpvh to use the counter generated address easy to achieve on the RAM read and write operations. Th value as the row address them with, tcph [9:4] as the column address, tcph [1: O] as the color of the address.
4 Conclusion
    Memory at a reasonable arrangement and design of the ranks of the counter based on timing control cleverly done and the liquid crystal display memory read and write data to achieve 8 of AT056TN04 basic colors of the display control. As a result of FPGA design, a slightly modified form can be applied to other soft-core LCD tft module, Color overcome the monotonous monochrome LCD module, and the color rich digital color screen expensive shortcomings. Of color in less demanding industrial instrumentation has a certain value.